1. Field of the Invention
The present invention relates to an exposure apparatus for exposing a substrate to radiant energy.
2. Description of the Related Art
Along with micropatterning and an increase in the density of circuits, exposure apparatus for manufacturing semiconductor devices is required to project circuit patterns from reticle surfaces onto substrate surfaces by exposure are required to have ever higher resolving powers. The projection resolving power of the circuit pattern depends on the numerical aperture (NA) of the projection optical system and the exposure wavelength. In view of this, the resolution is increased by adopting a method of increasing the NA of the projection optical system and a method of further shortening the exposure wavelength. In the method of further shortening the exposure wavelength, the wavelength of the exposure light source is shifting from the g-line to the i-line and from the i-line to even the oscillation wavelengths of excimer lasers. Exposure apparatuses having excimer lasers with oscillation wavelengths of 248 nm and 193 nm have already been put into practical use. At present, an exposure scheme using EUV (Extreme Ultra Violet) light with a wavelength of 13 nm is considered to be a candidate for a next-generation exposure scheme.
At the same time, the semiconductor device manufacturing process is diversifying. For example, a chemical mechanical polishing (CMP) process is receiving a great deal of attention as a planarization technique which solves the shortage of the depth of focus of the exposure apparatus. Various kinds of structures and materials of semiconductor devices are also proposed. Examples are a P-high electron mobility transistor and M-high electron mobility transistor formed by combining chemical compounds such as GaAs and InP, and a heterojunction bipolar transistor made of, for example, SiGe and SiGe.
Along with the micropatterning of circuits, another demand has arisen for accurately aligning a reticle on which a circuit pattern is formed and a substrate onto which it is projected. The necessary alignment accuracy is ⅓ the circuit line width. For example, the necessary alignment accuracy for the current 90-nm design is ⅓, that is, 30 nm.
Unfortunately, substrate alignment often causes a wafer-induced shift of the substrate in the manufacturing process, resulting in a decrease in the performance of a semiconductor device and in its manufacturing yield. In this specification, the wafer-induced shift will be referred to as a “WIS”. Examples of the WIS are the asymmetry of the structure of an alignment mark and the asymmetry of the shape of a resist applied to a substrate, due to the influence of a planarization process such as CMP. Furthermore, since a semiconductor device is manufactured via a plurality of processes, the optical condition of the alignment mark changes for each process, resulting in a variation in the amount of WIS for each process. To deal with this problem, it is necessary to prepare a plurality of measurement conditions for a plural number of times of alignment to determine an optimal measurement condition for each process. In the conventional substrate alignment, a substrate is actually exposed to light under several measurement conditions and undergoes overlay inspection to determine the measurement condition under which the best result of overlay inspection is obtained. However, this method takes a long period of time to determine the measurement condition. Japanese Patent Laid-Open No. 4-32219 proposes a method of determining the measurement condition using a “value obtained by quantifying the asymmetry or contrast of an alignment mark signal” as an index without overlay inspection. In this specification, a feature value associated with the measurement accuracy calculated from an alignment mark signal, such as the “value obtained by quantifying the asymmetry or contrast of an alignment mark signal” will be referred to as a “feature value”.
The measurement condition determination method described in Japanese Patent Laid-Open No. 4-32219 determines the measurement condition using the average of feature values within the substrate surface and their variation as indices. However, since measurement errors are generated at an actual device manufacturing site due to the shift/magnification/rotation of the substrate, it is difficult for the conventional indices to associate them with a WIS which actually poses a problem. This makes it impossible to determine a measurement condition under which the WIS has little influence.